Avago Technologies LSI53C1030 - Manual (Page 81)

Power-On Sense Pins Description 3-21
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
3.10 Power-On Sense Pins Description
In addition to providing the address/data bus for the external memory
interface, MAD[15:0] and MADP[1:0] provide eighteen Power-On Sense
pins that configure global operating conditions within the LSI53C1030.
The MAD[15:0] and MADP[1:0] pins have internal pull-down current sinks
and sense a logical 0 if no pull-up resistor is present on the pin. To
program a particular option, allow the internal pull-down to pull the pin
LOW or connect a 4.7 k
Ω
resistor between the appropriate pin and VDD
to pull the pin HIGH. The LSI53C1030 samples these pins during PCI
reset and holds their values upon the removal of PCI reset.
Table 3.20
provides the MAD Power-On Sense pin configuration options. LSI Logic
expects most configurations to employ the default settings. Provide
pull-up options for all MAD pins.
Table 3.20 MAD Power-On Sense Pin Options
MAD Pin Function Pulled-Down (Default) Pulled-Up
MADP[1] Reserved
MADP[0] PCI-X Mode Enables the PCI-X Mode. Disables the PCI-X Mode.
MAD[15] 133 MHz PCI-X Enables 133 MHz PCI-X Mode. Disables 133 MHz PCI-X Mode.
MAD[14] 64-bit PCI Configures a 64-bit PCI Bus. Configures a 32-bit PCI Bus.
MAD[13] 66 MHz PCI Enables the 66 MHz PCI Mode. Disables the 66 MHz PCI Mode.
MAD[12] Reserved
MAD[11] ID Control [1] Has no effect. Sets bit [15] of the PCI Function
[1]
Subsystem ID register to 0b1.
MAD[10] ID Control [0] Has no effect. Sets bit [15] of the PCI Function
[0]
Subsystem ID register to 0b1.
MAD[9:8] Reserved
MAD[7] Serial EEPROM
Download
Enable Enables the download of the PCI
configuration information from
the serial EEPROM. Disables the download of the PCI
configuration information from the
serial EEPROM.
MAD[6] IOP Boot Enable Enables the IOP boot process. Disables the IOP boot process.
MAD[5:4] PCI/SCSI
Configuration Configures the LSI53C1030 according to Table 3.21 .