Avago Technologies LSI53C1030 User Manual

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2-12

Functional Description

Version 2.2

2.3.2.8 Alias to Memory Read Block Command

This command is reserved for future implementations of the PCI
specification. The LSI53C1030 never generates this command as a
master. When a slave, the LSI53C1030 supports this command using the
Memory Read Block command.

2.3.2.9 Alias to Memory Write Block Command

2.3.2.10 Configuration Read Command

The Configuration Read command reads the configuration space of a
device. The LSI53C1030 never generates this command as a master, but
does respond to it as a slave. A device on the PCI bus selects the
LSI53C1030 by asserting its IDSEL signal when AD[1:0] equal 0b00.
During the address phase of a configuration cycle, AD[7:2] address one
of the 64 Dword registers in the configuration space of each device.
C_BE[3:0]/ address the individual bytes within each Dword register and
determine the type of access to perform. Bits AD[10:8] address either the
PCI Function [0] Configuration Space (AD[10:8] = 0b000) or the PCI
Function [1] Configuration Space (AD[10:8] = 0b001). The LSI53C1030
treats AD[63:11] as logical don’t cares.

2.3.2.11 Configuration Write Command

The Configuration Write command writes the configuration space of a
device. The LSI53C1030 never generates this command as a master, but
does respond to it as a slave. A device on the PCI bus selects the
LSI53C1030 by asserting its IDSEL signal when bits AD[1:0] equal 0b00.
During the address phase of a configuration cycle, bits AD[7:2] address
one of the 64 Dword registers in the configuration space of each device.
C_BE[3:0]/ address the individual bytes within each Dword register and
determine the type of access to perform. Bits AD[10:8] decode either the
PCI Function [0] Configuration Space (AD[10:8] = 0b000) or the PCI
Function [1] Configuration Space (AD[10:8] = 0b001). The LSI53C1030
treats AD[63:11] as logical don’t cares.