Avago Technologies LSI53C1030 User Manual
Page 114
4-28
PCI Host Register Description
Version 2.2
Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
Bus Number
[15:8]
These read only bits indicate the number of the
LSI53C1030 bus segment. This PCI function uses this
number as part of its Requester ID and Completer ID.
This field is read for diagnostic purposes only.
Device Number
[7:3]
These read only bits indicate the device number of the
LSI53C1030. This PCI function uses this number as part
of its Requester ID and Completer ID. This field is read
for diagnostic purposes only.
Function Number
[2:0]
These read only bits indicate the number in the Function
Number field (AD[10:8]) of a Type 0 PCI configuration
transaction. The PCI function uses this number as part of
its Requester ID and Completer ID. This field is read for
diagnostic purposes only.
4.2 PCI I/O Space and Memory Space Register Description
This section describes the host interface registers in the PCI I/O Space
and PCI Memory Space. These address spaces contain the Fusion-MPT
interface register set. PCI Memory Space [0] and PCI Memory Space [1]
form the PCI Memory Space. PCI Memory [0] supports normal memory
accesses while PCI Memory Space [1] supports diagnostic memory
accesses. For all registers except the
and
registers, access the address offset
through either PCI I/O Space or PCI Memory Space [0]. Access to the
and
registers is only through PCI I/O Space.
When the LSI53C1030 operates as a multifunction PCI device, the entire
PCI Memory and PCI I/O Space register sets are visible to both PCI
functions. When the LSI53C1030 operates as a single function PCI
device, only PCI Function [0] register sets are accessible. Refer to
Section 3.10, “Power-On Sense Pins Description,”
for information on how
to configure the LSI53C1030 as a single or multifunction PCI device.
defines the PCI I/O Space address map.