Avago Technologies LSI53C1030 User Manual
Page 82
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Signal Description
Version 2.2
Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
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MADP[1], Reserved.
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MADP[0], PCI-X Mode – By default, internal logic pulls this pin LOW
to enable the PCI-X mode on the LSI53C1030. Pulling this pin HIGH
disables the PCI-X mode on the LSI53C1030. Pull this pin HIGH when
the host board does not support the PCI-X mode. The setting of this
pin must coincide with the setting of the PCI_CAP pin on the host
board. When the PCI-X mode is disabled, the PCI-X extended
capabilities register structure is not visible in PCI Configuration Space.
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MAD[15], 133 MHz PCI-X – By default, internal logic pulls this pin
LOW to enable 133 MHz PCI-X operation and to set the 133 MHz
Capable bit in the
register. Pulling this pin HIGH
disables 133 MHz PCI-X operation and clears the 133 MHz Capable
bit in the
register.
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MAD[14], 64-bit PCI – By default, internal logic pulls this pin LOW
to enable 64-bit PCI operation and to set the 64-bit Enable bit in the
register. Pulling this pin HIGH configures the PCI
connection as a 32-bit connection and clears the 64-bit Enable bit in
the
register.
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MAD[13], 66 MHz PCI – By default, internal logic pulls this pin LOW
to enable 66 MHz PCI operation on the LSI53C1030 and to set the
66 MHz Capable bit in the PCI
register. Pulling this pin HIGH
disables 66 MHz PCI operation and clears the 66 MHz Capable bit
in the PCI
register.
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MAD[12], Reserved.
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MAD[11], ID Control [1] – By default, internal logic pulls this pin
LOW. Pulling this signal LOW either allows the serial EEPROM to
program bit 15 of the PCI Function [1]
register or allows
this bit to default to 0b0. Pulling this pin HIGH sets this bit to 0b1.
MAD[3]
NVSRAM Select
Has no effect.
Configures the LSI53C1030 to
support an NVSRAM.
MAD[2:1]
Flash ROM Size
Configures the Flash ROM size according to
MAD[0]
Reserved
Table 3.20
MAD Power-On Sense Pin Options (Cont.)
MAD Pin
Function
Pulled-Down (Default)
Pulled-Up