Avago Technologies LSI53C1030 - Manual (Page 157)

Index IX-3
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
record 2-27 , 2-28
space 2-8 , 4-1
write command 2-8 , 2-10 , 2-12 , 2-13 , 4-6
configuration space 2-8 , 4-1
C_BE[3:0]/ 2-10
context manager 2-5 , 2-6
core voltage 5-2 , 5-3
CRC 1-2 , 1-7 , 1-13 , 2-22
CRC-32 1-7
current
I/O supply 5-2
latch-up 5-2 , 5-8
cyclic redundancy check 1-2 , 2-22
D
D0 2-16 , 2-17 , 4-19
D1 2-16 , 2-17 , 4-19
D1 support bit 4-18
D2 2-16 , 2-17 , 4-19
D2 support bit 4-18
D3 2-16 , 2-17 , 2-18 , 4-19
DAC 1-11 , 2-8 , 2-10 , 2-13
data
diagnostic read/write 4-33
EEPROM 3-16
parity error recovery enable bit 4-26
parity error reported bit 4-6
scale bit 4-19
select bit 4-19
datapath engine 2-6
DC characteristics 5-1
debug signals 3-17
delay filter 5-8
designed maximum cumulative read size bit 4-26
designed maximum memory read byte count bit 4-27
designed maximum outstanding split transactions bit
4-26
detected parity error (from slave) bit 4-5
device complexity bit 4-27
device driver stability 1-6
device ID register 4-3
device number bit 4-28
device specific initialization bit 4-18
DEVSEL/ 3-6 , 5-5
DEVSEL/ timing bit 4-5
diagnostic memory 4-28
diagnostic memory enable bit 4-32
diagnostic read/write address register 4-31 , 4-32 , 4-34
diagnostic read/write data register 4-31 , 4-32 , 4-33 ,
4-34
diagnostic read/write enable bit 4-32
diagnostic write enable bit 4-31 , 4-34
DIS_PCI_FSN/ 3-18 , 3-25 , 5-6
DIS_SCSI_FSN/ 3-18 , 3-25 , 5-6
DisARM bit 4-32
DMA 1-12 , 2-4 , 2-6 , 2-15
arbiter and router 2-4
domain validation 1-2 , 1-8 , 1-13 , 2-22
doorbell 2-6 , 2-7
host 4-30
interrupt mask bit 4-37
status bit 4-35
system 4-30 , 4-35
system interface 2-6
system interrupt bit 4-35
double transition clocking 1-2 , 2-18
drawing
mechanical 5-26
package 5-18 , 5-20
drive strength 1-8 , 2-20 , 2-22
driver
LVD 5-3
DT clocking 1-2 , 2-18
DT data phase 2-18
dual address cycles command 1-11 , 2-8 , 2-10 , 2-13
E
EEPROM 2-5 , 2-6 , 2-27 , 3-16 , 3-23 , 3-25
configuration record 2-27
download enable 3-21
interface 2-27 , 3-16
electrostatic discharge 5-2
enable
bus mastering bit 4-4
diagnostic memory bit 4-32
diagnostic write bit 4-31
I/O space bit 4-5
memory space bit 4-4
MSI bit 4-22
parity error response bit 4-4
write and invalidate bit 4-4
ESD 1-13 , 5-2 , 5-8
expansion ROM base address 4-4
expansion ROM base address register 4-14
expansion ROM enable bit 4-14
external
clock 5-9
memory controller 2-5
memory interface 2-24
memory interface timing diagrams 5-11
F
ferrite bead 3-20
fibre channel 1-5 , 1-12