Avago Technologies LSI53C1030 - Manual (Page 54)

2-24 Functional Description
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
2.5 External Memory Interface
The LSI53C1030 provides Flash ROM, NVSRAM, and serial EEPROM
interfaces. The Flash ROM interface stores the SCSI BIOS and firmware
image. The Flash ROM is optional if the LSI53C1030 is not the boot
device and a suitable driver exists to initialize the LSI53C1030. Integrated
Mirroring (IM) technology requires an NVSRAM for write journaling. The
nonvolatile external serial EEPROM stores configuration parameters for
the LSI53C1030.
2.5.1 Flash ROM Interface
The Flash ROM interface multiplexes the 8-bit address and data buses
on the MAD[7:0] pins. The interface latches the address into three 8-bit
latches to support up to 1 Mbyte of address space. The interface
supports byte, word, and Dword accesses. The LSI53C1030 Dword
aligns Dword reads, word aligns word reads, and byte aligns byte reads.
The remaining bits from word and byte reads are meaningless.
The MAD[2:1] Power-On sense pin configurations define the size of the
Flash ROM address space.
Table 2.3 provides the pin encoding for these
pins. By default, internal logic pulls these pins down to indicate that no
Flash ROM is present.
The LSI53C1030 defines only the middle (MA[15:8]) and lower (MA[7:0])
address ranges if the Flash ROM addressable space is 64 Kbytes or
less. The LSI53C1030 defines the upper (MA[21:16]), middle (MA[15:8]),
and lower (MA[7:0]) address ranges if the Flash ROM addressable space
Table 2.3 Flash ROM Size Programming
MAD[2:1] Options Flash ROM Size
0b00 No Flash ROM present (Default)
0b01 Up to 1024 Kbytes
1
1. Choose this setting for a 128 Kbyte or 512 Kbyte Flash ROM.
0b10
Reserved
0b11