Avago Technologies LSI53C1030 User Manual

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2-14

Functional Description

Version 2.2

2.3.2.15 Memory Read Line Command

This command is identical to the Memory Read command except it
additionally indicates that the master intends to fetch a complete cache
line. The LSI53C1030 supports this command when operating in the PCI
mode.

2.3.2.16 Memory Read Block Command

The LSI53C1030 uses this command to read from memory. The
LSI53C1030 supports this command when operating in the PCI-X mode.

2.3.2.17 Memory Write and Invalidate Command

The Memory Write and Invalidate command is identical to the Memory
Write command, except it additionally guarantees a minimum transfer of
one complete cache line. The master uses this command when it intends
to write all bytes within the addressed cache line in a single PCI
transaction unless interrupted by the target. This command requires
implementation of the PCI

Cache Line Size

determines when to issue a Write and Invalidate command instead of a
Memory Write command and supports this command when operating in
the PCI bus mode.

Alignment – The LSI53C1030 uses the calculated line size value to
determine if the current address aligns to the cache line size. If the
address does not align, the LSI53C1030 bursts data using a noncache
command. If the starting address aligns, the LSI53C1030 issues a
Memory Write and Invalidate command using the cache line size as the
burst size.

Multiple Cache Line Transfers – The Memory Write and Invalidate
command can write multiple cache lines of data in a single bus
ownership. The LSI53C1030 issues a burst transfer as soon as it
reaches a cache line boundary. The PCI Local Bus specification states
that the transfer size must be a multiple of the cache line size. The
LSI53C1030 selects the largest multiple of the cache line size based on
the transfer size. When the DMA buffer contains less data than the value

Cache Line Size

Write command on the next cache boundary to complete the data
transfer.