Avago Technologies LSI53C1030 - Manual (Page 43)

PCI Functional Description 2-13
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
2.3.2.12 Memory Read Multiple Command
The Memory Read Multiple command is identical to the Memory Read
command, except it additionally indicates that the master intends to fetch
multiple cache lines before disconnecting. The LSI53C1030 supports PCI
Memory Read Multiple functionality when operating in the PCI mode and
determines when to issue a Memory Read Multiple command instead of
a Memory Read command.
Burst Size Selection – The Read Multiple command reads multiple
cache lines of data during a single bus ownership. The number of cache
lines the LSI53C1030 reads is a multiple of the cache line size, which
Revision 2.2 of the PCI specification provides. The LSI53C1030 selects
the largest multiple of the cache line size based on the amount of data
to transfer.
2.3.2.13 Split Completion Command
Split transactions in PCI-X replace the delayed transactions in
conventional PCI. The LSI53C1030 supports up to eight outstanding split
transactions when operating in the PCI-X mode. A split transaction
consists of at least two separate bus transactions: a split request, which
the requester initiates, and one or more split completion commands,
which the completer initiates. Revision 1.0a of the PCI-X addendum
permits split transaction completion for the Memory Read Block, Alias to
Memory Read Block, Memory Read Dword, Interrupt Acknowledge,
I/O Read, I/O Write, Configuration Read, and Configuration Write
commands. When operating in the PCI-X mode, the LSI53C1030
supports the Split Completion command for all of these commands
except the Interrupt Acknowledge command, which the LSI53C1030
neither responds to nor generates.
2.3.2.14 Dual Address Cycles (DAC) Command
The LSI53C1030 performs Dual Address Cycles (DAC), per the PCI
Local Bus Specification, Revision 2.2. The LSI53C1030 supports this
command when operating in either the PCI or PCI-X bus mode.