Avago Technologies LSI53C1030 - Manual (Page 105)

PCI Configuration Space Register Description 4-19
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
Register: 0xXX
Power Management Control/Status
Read/Write
PME_Status 15
The PCI function clears this bit since the LSI53C1030
does not support PME signal generation from D3
cold
.
Data_Scale [14:13]
The PCI function clears these bits since the LSI53C1030
does not support the Power Management Data register.
Data_Select [12:9]
The PCI function clears these bits since the LSI53C1030
does not support the Power Management Data register.
PME_Enable 8
The PCI function clears this bit since the LSI53C1030
does not provide a PME signal and disables PME asser-
tion.
Reserved [7:2]
This field is reserved.
Power State [1:0]
These bits determine the current power state of the
LSI53C1030. Power states are:
15 14 13 9 8 7 2 1 0
Power Management Control/Status
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0b00 D0
0b01 D1
0b10 D2
0b11 D3
hot