Avago Technologies LSI53C1030 - Manual (Page 88)

4-2 PCI Host Register Description
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
Interrupts, and PCI-X) to optimize device performance. The LSI53C1030
does not hard code the location and order of the PCI extended capability
structures. The address and location of the PCI extended capability
structures are subject to change. To access a PCI extended capability
structure, follow the pointers held in the Capability Pointer registers and
identify the extended capability structure with the Capability ID register
for the given structure.
Table 4.1 LSI53C1030 PCI Configuration Space Address Map
31 16 15 0 Offset Page
Device ID Vendor ID 0x00 4-3
Status Command 0x04 4-3
Class Code Revision ID 0x08 4-7
Reserved Header Type Latency Timer Cache Line Size 0x0C 4-7
I/O Base Address 0x10 4-9
Memory [0] Low 0x14 4-9
Memory [0] High 0x18 4-10
Memory [1] Low 0x1C 4-10
Memory [1] High 0x20 4-11
Reserved
0x24 –
0x28 –
Subsystem ID Subsystem Vendor ID 0x2C 4-12
Expansion ROM Base Address 0x30 4-14
Reserved
Capabilities Pointer 0x34 4-14
0x38 –
Maximum Latency Minimum Grant Interrupt Pin Interrupt Line 0x3C 4-15
Reserved
0x40–
0x7F
–
Power Management Capabilities PM Next Pointer PM Capability ID 4-17
PM Data PM BSE Power Management Control/Status 4-19
Reserved –
Message Control MSI Next Pointer MSI Capability ID 4-21
Message Address 4-22
Message Upper Address 4-23
Message Data 4-23
Reserved –
PCI-X Command PCI-X Next Pointer PCI-X Capability ID 4-24
PCI-X Status 4-26
Reserved –