Power management capabilities, Register: 0xxx – Avago Technologies LSI53C1030 User Manual
Page 104
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PCI Host Register Description
Version 2.2
Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
Register: 0xXX
Power Management Capabilities
Read Only
PME_Support
[15:11]
These bits define the power management states in which
the device asserts the Power Management Event (PME)
pin. The LSI53C1030 clears these bits since the
LSI53C1030 does not provide a PME signal.
D2_Support
10
The PCI function sets this bit since the LSI53C1030 sup-
ports power management state D2.
D1_Support
9
The PCI function sets this bit since the LSI53C1030 sup-
ports power management state D1.
Aux_Current
[8:6]
The PCI function clears this field since the LSI53C1030
does not support Aux_Current.
Device Specific Initialization
5
The PCI function clears this bit since no special initializa-
tion is required before a generic class device driver can
use it.
Reserved
4
This bit is reserved.
PME Clock
3
The LSI53C1030 clears this bit since the chip does not
provide a PME pin.
Version
[2:0]
The PCI function programs these bits to 0b010 to indicate
that the LSI53C1030 complies with the PCI Power Man-
agement Interface Specification, Revision 1.1.
15
11
10
9
8
7
6
5
4
3
2
0
Power Management Capabilities
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
0