Avago Technologies LSI53C1030 - Manual (Page 152)

A-2 Register Summary
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
Expansion ROM Base Address 0x30–0x33 Read/Write 4-14
Capabilities Pointer 0x34 Read Only 4-14
Reserved 0x35–0x37; 0x38–0x3B Reserved 4-15
Interrupt Line 0x3C Read/Write 4-15
Interrupt Pin 0x3D Read Only 4-16
Minimum Grant 0x3E Read Only 4-16
Maximum Latency 0x3F Read Only 4-17
Power Management Capability ID — Read Only 4-17
Power Management Next Pointer — Read Only 4-17
Power Management Capabilities — Read Only 4-18
Power Management Control/Status — Read/Write 4-19
Power Management Bridge Support Extensions — Read Only 4-20
Power Management Data — Read Only 4-20
MSI Capability ID — Read Only 4-20
MSI Next Pointer — Read Only 4-21
Message Control — Read/Write 4-21
Message Address — Read/Write 4-22
Message Upper Address — Read/Write 4-23
Message Data — Read/Write 4-23
PCI-X Capability ID — Read Only 4-24
PCI-X Next Pointer — Read Only 4-24
PCI-X Command — Read/Write 4-24
PCI-X Status — Read/Write 4-26
1. The offset of the PCI extended capabilities registers can vary. Access these registers through the
Next Pointer and Capability ID registers.
Table A.1 LSI53C1030 PCI Registers (Cont.)
Register Name Offset
1
Read/Write Page