Avago Technologies LSI53C1030 - Manual (Page 112)

4-26 PCI Host Register Description
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
Data Parity Error Recovery Enable 0
The host device driver sets this bit to allow the
LSI53C1030 to attempt to recover from data parity errors.
If the user clears this bit and the LSI53C1030 is operating
in the PCI-X mode, the LSI53C1030 asserts SERR/
whenever the Master Data Parity Error bit in the PCI
Sta-
tus register is set.
Register: 0xXX
PCI-X Status
Read/Write
Reserved [31:30]
This field is reserved.
Received Split Completion Error Message 29
The LSI53C1030 sets this bit upon receipt of a split com-
pletion message if the split completion error attribute bit
is set. Write a one (1) to this bit to clear it.
Designed Maximum Cumulative Read Size [28:26]
These read only bits indicate a number greater than or
equal to the maximum cumulative size of all outstanding
burst memory read transactions for the LSI53C1030 PCI
device. The PCI function must report the smallest value
that correctly indicates its capability. The LSI53C1030
reports 0b001 in this field to indicate a designed maxi-
mum cumulative read size of 2 Kbytes.
Designed Maximum Outstanding
Split Transactions
[25:23]
These read only bits indicate a number greater than or
equal to the maximum number of all outstanding split
transactions for the LSI53C1030 PCI device. The PCI
function must report the smallest value that correctly indi-
cates its capability. The LSI53C1030 reports 0b100 in this
field to indicate that the designed maximum number of
outstanding split transactions is eight.
31 30 29 28 27 26 25 23 22 21 20 19 18 17 16 15 8 7 3 2 0
PCI-X Status
0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 1 X X X X X X X X X X X X X X X X