Avago Technologies LSI53C1030 - Manual (Page 116)

4-30 PCI Host Register Description
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
Register: 0x00
System Doorbell
Read/Write
The System Doorbell register is a simple message passing mechanism
that allows the system to pass single word messages to the embedded
IOP processor and vice-versa. There is a unique system doorbell for
each PCI function.
When a host system PCI master writes to the Host Registers->Doorbell
register, the LSI53C1030 generates a maskable interrupt to the IOP. The
value written by the host system is available for the IOP to read in the
System Interface Registers->Doorbell register. The IOP clears the
interrupt status after reading the value.
Conversely, when the IOP processor writes to the System Interface
Registers->Doorbell register, the LSI53C1030 generates a maskable
interrupt to the PCI system. The host system can read the value written
by the IOP in the Host Registers->Doorbell register. The host system
clears the interrupt status bit and interrupt pin by writing any value to the
Host Registers->Interrupt Status register.
Host Doorbell Value [31:0]
During a write, this register contains the doorbell value
that the host system passes to the IOP. During a read,
this register contains the doorbell value that the IOP
passes to the host system.
Register: 0x04
Write Sequence
Read/Write
The Write Sequence register provides a protection mechanism against
inadvertent writes to the
Host Diagnostic register. There is one Write
31 0
System Doorbell
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
31 4 3 0
Write Sequence
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1