Avago Technologies LSI53C1030 - Manual (Page 39)

PCI Functional Description 2-9
Version 2.2 Copyright © 2001, 2002, 2003 by LSI Logic Corporation. All rights reserved.
Bits AD[7:2] select one of the sixty-four Dword registers in the device’s
PCI Configuration Space. Bits AD[1:0] determine if the configuration
command is a Type 0 Configuration Command (AD[1:0] = 0b00) or a
Type 1 Configuration Command (AD[1:0] = 0b01). Since the LSI53C1030
is not a PCI Bridge device, all PCI Configuration Commands designated
for the LSI53C1030 must be Type 0. C_BE[3:0]/ address the individual
bytes within each Dword and determine the type of access to perform.
2.3.1.2 PCI I/O Space
The PCI specification defines I/O Space as a contiguous 32-bit I/O
address that all system resources share, including the LSI53C1030. The
I/O Base Address register determines the 256-byte PCI I/O area that the
PCI device occupies.
2.3.1.3 PCI Memory Space
The LSI53C1030 contains two PCI memory spaces: PCI Memory
Space [0] and PCI Memory Space [1]. PCI Memory Space [0] supports
normal memory accesses, while PCI Memory Space [1] supports
diagnostic memory accesses. The LSI53C1030 requires 64 Kbytes of
memory space.
The PCI specification defines memory space as a contiguous 64-bit
memory address that all system resources share. The
Memory [0] Low
and Memory [0] High registers determine which 64 Kbyte memory area
PCI Memory Space [0] occupies. The Memory [1] Low and Memory [1]
High registers determine which 64 Kbyte memory area PCI Memory
Space [1] occupies.
2.3.2 PCI Commands and Functions
Bus commands indicate to the target the type of transaction the master
is requesting. The master encodes the bus commands on the C_BE[3:0]/
lines during the address phase. The PCI bus command encodings
appear in
Table 2.1 .