FUJITSU F2MC-8L F202RA - Manual (Page 270)

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CHAPTER 11 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL)
11.6 Operations of External Interrupt Circuit 2
External interrupt circuit 2 detects "L" level at any of the external interrupt pins, then
generates and issues an interrupt request to the CPU.
■ Operation of External Interrupt Circuit 2
To operate the external interrupt circuit 2, the bits of the registers must be set as shown in Figure 11.6-1 .
Figure 11.6-1 Setting External Interrupt Circuit 2
When an "L" level signal is input to an external interrupt pin among the pins INT20 to INT27 with external
interrupt inputs being enabled by one of the IE20 to IE27 bits corresponding to the pin, external interrupt
circuit 2 generates and issues an IRQA interrupt request to the CPU.
Figure 11.6-2 shows the operation of external interrupt circuit 2 (when the INT20/AN4 pin is used).
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
EIE2 IE27 IE26 IE25 IE24 IE23 IE22 IE21 IE20
EIF2 IF20
DDR0
ADEN
: Used bit
: Unused bit
0 : Set "0"
0 0 0 0
0 0 0 0 0 0 0 0