FUJITSU F2MC-8L F202RA - Manual (Page 232)

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CHAPTER 9 12-BIT PPG TIMER
9.4.3 12-bit PPG Control Register 3 (RCR23)
The 12-bit PPG control register 3 comprises a bit for enabling 12-bit PPG waveform
outputs and bits for setting a cycle period of outputs.
■ 12-bit PPG Control Register 3 (RCR23)
Figure 9.4-4 12-bit PPG Control Register 3 (RCR23)
SCL5 to SCL0
XXXXXX
RCEN
0
1
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
0016 H RCEN SCL5 SCL4 SCL3 SCL2 SCL1 SCL0 0-000000
B
R/W R/W R/W R/W R/W R/W R/W
R/W
Address Initial value
Cycle period setting bits
Compare value for the cycle period of 12-bit PPG output
Output enable bit
Output disabled, counter cleared
Output enabled with count operation starting
: Readable/Writable
: Unused
: Initial value