FUJITSU F2MC-8L F202RA - Manual (Page 67)

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CHAPTER 3 CPU
3.6 Clock
The clock generator includes the oscillation circuit. A high-speed clock is generated by
connecting an external resonator for oscillation frequency. Alternatively, when the
clock is supplied from an external source, a clock signal can be connected to the clock
input pin.
The clock controller manages the speed and supply of the clock in active mode and
standby mode.
■ Clock Supply Map
The clock controller manages oscillation of the clock and provision of the clock to the CPU and peripheral
circuits (peripheral functions). Thus, the operating clock for the CPU or peripheral circuits is affected by
clock speed switching (gears) and setting in standby mode (sleep/stop).
To peripheral functions, a divided frequency output of the free-run counter operating with the clock for
peripheral circuits is provided.
However, the divided frequency output of the time-base timer operating with 1/2 frequency of the
oscillation frequency is not affected by the gear.
Figure 3.6-1 shows the clock supply map.