FUJITSU F2MC-8L F202RA - Manual (Page 250)

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CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 1 (EDGE)
bit0
EIE0:
Interrupt request
enable bit 0
This bit enables or disables interrupt request outputs to the CPU. When this bit and
external interrupt request flag bit 0 (EIR0) are "1", the interrupt request is output.
Notes:
•
When using the external interrupt pin, write "0" for bit4 of the port data direction
register (DDR3) so that the pin serves inputs only. Write "0" for bit1 of the timer
output control register (TCR2) for the 8/16-bit capture timer/counter to set the
port input function on.
• Regardless of the interrupt request enable bit state, the state of the external
interrupt pin can be read directly from the port data register (PDR3).
Table 10.4-1 Explanation of Functions of Each Bit in External Interrupt Control Register 1 (EIC1) (2/2)
Bit name Function