FUJITSU F2MC-8L F202RA - Manual (Page 314)

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CHAPTER 13 UART
13.4.5 Serial Output Data Register (SODR)
The serial output data register (SODR) sends out (transmits) serial data.
■ Serial Output Data Register (SODR)
Figure 13.4-7 shows the configuration of the serial output data register bits.
Figure 13.4-7 Serial Output Data Register (SODR)
When transmission is enabled, writing data to be transmitted into this register after reading the SSD register
sends the data to be transmitted to the transmission shift register, converts it into the serial format, then
outputs it from the serial data output pin (UO pin).
When the transmitted data is written into the SODR register, the transmitted data flag bit is cleared with
"0". After the transmitted data is sent to the transmission shift register, the transmitted data flag bit is set to
"1", the data transmitted next then becomes writable. At this time, if the transmission interrupt request is
enabled, an interrupt is generated. Write the data transmitted next when a transmission interrupt occurs or
while the transmitted data flag bit is "1".
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
002B
H
XXXXXXXX
B
W W W W W W W W
W
X
Address Initial value
: Write only
: Undefined