FUJITSU F2MC-8L F202RA - Manual (Page 140)

124
CHAPTER 5 TIME-BASE TIMER
5.6 Notes on Using Time-base Timer
Notes on using the time-base timer are shown below.
■ Notes on Using Time-base Timer
● Notes on using programs to set time-base timer
When the interrupt request flag bit (TBTC: TBOF) is "1" and the interrupt request enable bit is enabled
(TBTC: TBIE = 1), a return from interrupt handling is not possible. The TBOF bit must be cleared.
●
Clearing time-base timer
The time-base timer is cleared when the time-base timer initialization bit is set to 0 (TBTC: TBR = 0) or
when the oscillation stabilization time is required. Because the time-base timer is used as the count clock
for the watchdog timer, clearing the time-base timer also clears the watchdog timer.
●
Using time-base timer as oscillation stabilization time timer
Oscillation has not yet started in stop mode or when the power is turned on. Therefore, the time-base timer
makes oscillation stabilization wait time after the resonator starts operating.
The appropriate oscillation stabilization time must be selected according to the type of resonator connected
to the resonator (clock generator).
See Section "3.6.1 Clock Generator ".
● Notes on peripheral functions the time-base timer supplies to the clock
When entering the modes in which oscillation stops, the counter is cleared and the time-base timer stops
operating. The clock from the time-base timer may have a shorter "H" level period or longer "L" level
period (up to half the clock cycle) when the counter of the time-base timer is cleared because the clock
starts operating from the initial state. The clock for the watchdog timer also starts operating from the initial
state, but the watchdog timer operates at a normal cycle because the watchdog timer counter is cleared at
the same time.