FUJITSU F2MC-8L F202RA - Manual (Page 61)

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CHAPTER 3 CPU
3.5.1 Reset Flag Register (RSFR)
The reset flag register (RSFR) allows confirmation of the source for a generated reset.
■ Configuration of the Reset Flag Register (RSFR)
Figure 3.5-1 Configuration of Reset Flag Register (RSFR)
SFTR
0
1
WDOG
0
1
ERST
0
1
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
000E
H PONR ERST WDOG SFTR
XXXX----
B
R R R R
R : Read only
: Unused
X : Undefined
Address
Initial value
Software reset flag bit
When read
When read
When read
When written
When written
When written
The source is software reset.
PONR
0
1
When read When written
Does not affect
operations
Watchdog reset flag bit
Does not affect
operations
Does not affect
operations
Does not affect
operations
The source is watchdog reset.
External reset flag bit
The source is external reset.
Power-on reset flag bit
The source is power-on reset.