FUJITSU F2MC-8L F202RA - Manual (Page 54)

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CHAPTER 3 CPU
➃
The interrupt controller is always monitoring interrupt requests from peripheral functions. The interrupt
controller notifies the CPU of the highest interrupt level interrupt among levels corresponding to
interrupt requests currently generated. If different requests are made with the same interrupt level, the
interrupt controller also determines their priorities.
➄
The CPU checks the value in the interrupt enable flag (CCR: I) when the priority of the interrupt level
that is received is higher (the level value is lower) than the level specified in the interrupt level bits in
the condition code register (CCR: IL1 and IL0). The CPU then accepts the interrupt when the enable
flag is turned on (CCR: I = 1).
➅
Put the values in the program counter (PC) and program status (PS) in the stack, fetch the start address
of the interrupt processing routine from the interrupt vector table concerned, change the value of the
interrupt level bits in the condition code register (CCR: IL1 and IL0) to the value of the interrupt level
accepted, and then start the interrupt processing routine.
➆
Finally, restore the values of the program counter (PC) and program status (PS) put into the stack with
the RETI instruction, then execute an instruction following the instruction executed immediately before
the interruption.
Standby mode (low-power consumption mode) is cancelled by an interrupt. For details, see Section "3.7
Standby Mode (Low-Power Consumption Mode) ".
Notes:
• An interrupt request flag bit for a peripheral function is not automatically cleared even if the
interrupt request is accepted. Therefore, it is necessary to clear the bit using a program in the
interrupt processing routine (by writing "0" into the interrupt request flag bit normally).
• Clearing an interrupt request flag bit at the beginning of the interrupt processing routine allows the
peripheral function that generated the interrupt to re-generate an interrupt (set an interrupt request
flag bit again) while the interrupt processing routine is being executed. However, the re-generated
interrupt is normally accepted after the interrupt processing routine ends its current cycle.