FUJITSU F2MC-8L F202RA - Manual (Page 103)

87
CHAPTER 4 I/O PORTS
Table 4.3-3 lists the functions of port 3 registers.
●
Port 3 pull-up setting register (PUL3)
The bits of the pull-up setting register correspond to the pins of port 3 in one-to-one correspondence. When
the pull-up resistor is selected by using the pull-up setting register, the pin state will be "H" level (pull-up
state) instead of Hi-Z during stop (SPL = 1). During a reset, however, the pull-up is invalid and the pin
remains at Hi-Z.
Figure 4.3-2 shows the pull-up resistor settings assigned to the values of the bits of the port 3 pull-up
register.
Figure 4.3-2 Pull-up Setting Register (PUL3)
Table 4.3-3 Functions of Port 3 Registers
Register
name
Data
When being
read
When being written
Read/
Write
Address Initial value
Port 3 data
register
(PDR3)
0
Pin state is
"L" level.
Output latch of "0" is set and
"L" level is output to the pin in
output port mode.
R/W 000C
H
XXXXXXXX
B
1
Pin state is
"H" level.
Output latch of "1" is set and
"H" level is output to the pin in
output port mode.
Port 3 data
direction
register
(DDR3)
0
Read
prohibited
(write only)
Output transistor operation is
disabled and the pin is set to
serve as an input pin.
W 000D
H
00000000
B
1
Output transistor operation is
enabled and the pin is set to
serve as an output pin.
R/W : Readable and Writable
W
: Write only
X : Undefined
PUL33 PUL32 PUL31 PUL30
0
1
PUL37 PUL36 PUL35 PUL34
0
1
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
0071 H PUL37 PUL36 PUL35 PUL34 PUL33 PUL32 PUL31 PUL30 00000000 B
R/W R/W R/W R/W R/W R/W R/W R/W
R/W : Readable and Writable
: Initial value
Address Initial value
P33 pull-up OFF P32 pull-up OFF P31 pull-up OFF P30 pull-up OFF
P33 pull-up ON P32 pull-up ON P31 pull-up ON P30 pull-up ON
P37 pull-up OFF P36 pull-up OFF P35 pull-up OFF P34 pull-up OFF
P37 pull-up ON P36 pull-up ON P35 pull-up ON P34 pull-up ON