FUJITSU F2MC-8L F202RA - Manual (Page 114)

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CHAPTER 4 I/O PORTS
4.5.2 Operations of Port 5 Functions
This section describes the operation of port 5.
■ Operation of Port 5
●
Operation in output port mode
When "1" is written for a bit of the DDR5 register, the bit corresponding to the pin of port 5, the pin
functions as an output port.
In output port mode, the output transistor operation is enabled and the output latch data is output to the pin.
Once data has been written into the PDR5 register, the written data is held in the output latch and output to
the pin as it is.
The value state of the pin can be read by reading the PDR5 register.
●
Operation in input port mode
When "0" is written for a bit of the DDR5 register, the bit corresponding to the pin of port 5, the pin
functions as an input port.
In input port mode, the output transistor is OFF and the pin state is Hi-Z.
Once data has been written into the DDR5 register, the written data is held in the output latch but is not
output to the pin.
The value state of the pin can be read by reading the PDR5 register.
● Operation in mode enabling the output from a peripheral
When the output enable bit for a peripheral is set enable, the corresponding pin is set to serve the output
from the peripheral.
Because the value state of the pin can be read from the PDR5 register even when the output from the
peripheral is enabled, the value output from the peripheral can be read.
● Operation when a reset is performed
When the CPU is reset, the bits of the DDR5 register are initialized to "0". Thus, the output transistor
becomes OFF (input port mode) and the pin becomes Hi-Z.
However, CPU resets do not initialize the PDR5 register. If the pin is used as an output port after the reset,
reinitialize the PDR5 register to contain new output data in the bit position corresponding to the pin and
then set the corresponding bit of the DDR5 register so that the pin will function as an output port.
●
Operation in stop mode
When the pin state setting bit of the standby control register (STBC: SPL) is set to "1" and when the stop
mode is entered, the pin becomes Hi-Z because the output transistor is turned OFF regardless of the value
existing on the DDR5 register in the bit position corresponding to the pin. Input remains fixed to prevent
leaks by input open.