FUJITSU F2MC-8L F202RA - Manual (Page 389)

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CHAPTER 17 FLASH MEMORY
17.7 Notes on using Flash Memory
This section provides notes on using the MB89F202, especially for flash memory.
■ Input of a Hardware Reset (RST)
To input a hardware reset when reading is in progress, i.e., when the automatic algorithm has not been
started, secure a minimum low-level width of 1650 ns.
To input a hardware reset while a write or erase is in progress, i.e., while the automatic algorithm is being
started, secure a minimum low-level width of 1650 ns. In this case, 20
µs are required until the data
becomes readable after the operation being performed terminates and the flash memory is fully initialized.
Performing a hardware reset during a write operation makes the data being written undetermined. Also note
that performing a hardware reset or shut-down during an erase operation may make the sector from which
data is being erased unusable.
■ Software Reset, Watchdog Timer Reset
When write/erase of flash memory is set up for normal mode and CPU memory access mode is internal
ROM mode, and if a reset cause occurs while the automatic algorithm of flash memory is being activated,
the CPU may run out of control.
The cause of a reset does not initialize the flash memory and keeps the automatic algorithm operating.
Thus, when the CPU starts a sequence after the reset is cancelled, the flash memory may not have been in a
read state. Prevent a cause of a reset from occurring while the flash memory is writing or erasing.
■ Program Access to Flash Memory
While the automatic algorithm is being activated, any read access to the flash memory is disabled. When
CPU memory access mode is set to internal ROM mode, move program areas into another area such as
RAM, and then start a write or erase.
In this case, when the flash containing interrupt vectors are erased, the writing or erasing of interrupt
processing cannot be executed.
For the same reason, other interrupt processing shall be disabled while the automatic algorithm is being
activated.
■ Flash Content Protection
Flash content can be read using parallel / serial programmer if the flash content protection mechanism is
not activated.
One predefined area of the flash (FFFC
H
) is assigned to be used for preventing the read access of flash
content. If the protection code "01
H
" is written in this address (FFFC
H
), the flash content cannot be read by
any parallel / serial programmer.
Note : The program written into the flash cannot be verified once the flash protection code is written ("01
H
"
in FFFC
H
). It is advised to write the flash protection code at last.