FUJITSU F2MC-8L F202RA - Manual (Page 348)

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CHAPTER 14 8-BIT SERIAL I/O
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8-bit serial I/O operation at issuance of stop request during operation
As shown in Figure 14.8-6 , if operation is stopped (SMR: SST = 0) during data transfer, the 8-bit serial I/O
stops data transfer and clears the shift clock counter. For this reason, the transfer destination must also be
initialized. If serial output is in operation, set the SDR again before restarting the 8-bit serial I/O. In this
case, when the external clock is input, the SO pin output changes.
Figure 14.8-6 8-bit Serial I/O Operation at Issuance of Stop Request during Operation
(External Shift Clock)
#0 #1 #2 #4 #3 #5 #0 #1
#7 #6
SCK input
SST bit
Clock for the next data
Operation stop
SDR register resetting
Restart
SIOF bit
SO pin output