FUJITSU F2MC-8L F202RA - Manual (Page 145)

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CHAPTER 6 WATCHDOG TIMER
6.2 Configuration of Watchdog Timer
The watchdog timer consists of the following four function blocks.
• Watchdog timer counter
• Reset control circuit
• Counter clear control circuit
• Watchdog control register (WDTC)
■ Block Diagram of Watchdog Timer
Figure 6.2-1 Block Diagram of Watchdog Timer
● Watchdog timer counter (1-bit counter)
A 1-bit counter that operates by accepting output from the time-base timer as the count clock.
●
Reset control circuit
Sends the reset signal to the CPU when the watchdog timer counter overflows.
●
Counter clear control circuit
Controls the clearing and stopping of the watchdog timer counter.
● Watchdog control register (WDTC)
Activates and clears the watchdog timer counter. Because this register is write-only, bit manipulation
instructions cannot be used.
WTE 3 WTE2 WTE1 WTE0
R S T
W a tchdog control regi s ter (WDTC)
W a tchdog timer
Cle a r S t a rt
(Time-
bas e timer
o u tp u t)
1- b it co u nter
Overflow
Re s et
control
circ
u it
2 22 /F
CH