FUJITSU F2MC-8L F202RA - Manual (Page 89)

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CHAPTER 3 CPU
Figure 3.8-2 Operations for Selecting Memory Access
Wait for cancellation of
the reset source
(external reset or
oscillation stabilization
wait time)
Mode fetch
Check of the mode data
Setup of I/O pin
functions at execution
of program (RUN mode)
Source of a reset is generated.
I/O pins are high
impedance.
Being reset
Mode data and reset vector are
fetched from internal ROM.
Mode data
Other
settings
Prohibited
Single-chip mode (00
H
)
I/O settings for each I/O pin using
the port direction register (DDR)
and other measures
I/O pins are available
as ports.