FUJITSU F2MC-8L F202RA - Manual (Page 230)

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CHAPTER 9 12-BIT PPG TIMER
9.4.1 12-bit PPG Control Register 1 (RCR21)
The 12-bit PPG control register 1 comprises bits for count clock selection of the 12-bit
PPG timer and bits for setting the "H" width.
■ 12-bit PPG Control Register 1 (RCR21)
Figure 9.4-2 12-bit PPG Control Register 1 (RCR21)
H S C5 to H S C0
XXXXXX
RCK1 RCK0
0 0 2 t
IN S T
0 1 4 t
IN S T
1 0 16 t
IN S T
1 1 256 t
IN S T
b it7 b it6 b it5 b it4 b it 3 b it2 b it1 b it0
0014
H
RCK1 RCK0 H S C5 H S C4 H S C 3 H S C2 H S C1 H S C0 00000000
B
R/W R/W R/W R/W R/W R/W R/W R/W
R/W : Re a d ab le/Writ ab le
: Initi a l v a l u e
Addre ss Initi a l v a l u e
"H" width s etting b it s
Comp a re v a l u e for the "H" width of 12- b it PPG o u tp u t s .
Co u nt clock s election b it s
Table 9.4-1 Explanation of Functions of Each Bit in 12-bit PPG Control Register 1 (RCR21)
Bit name Function
bit7,
bit6
RCK1, RCK0:
Count clock
selection bits
These bits are used to select a count clock of the 12-bit PPG timer from four types of
internal count clocks.
bit5
to
bit0
HSC5 to HSC0:
"H" width setting
bits
These bits are used to set the number of counts corresponding to the "H" width of
12-bit PPG timer outputs (the compare value for the "H" width), and the contents of
these bits and the HSC6 to HSC11 bits of the RCR22 register are compared with a
count by the counter.