FUJITSU F2MC-8L F202RA - Manual (Page 342)

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CHAPTER 14 8-BIT SERIAL I/O
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Serial output operation using external shift clock
Serial output operation with the external shift clock requires the settings shown in Figure 14.6-2 .
Figure 14.6-2 Settings Required for Serial Output Operation using External Shift Clock
When serial output operation is allowed, the contents of the SDR are output to the SO pin in synchronization
with the falling edge of the external shift clock. When serial operation is completed, immediately reset the SDR,
set it again, then allow serial output operation (SMR: SST = 1) to prepare for the output of the next data.
When the remote serial input operation (rising edge) is completed and the 8-bit serial I/O enters the idle
state (state in which it waits for the output of the next data), set the external shift clock to a high level.
Figure 14.6-3 shows 8-bit serial output operation.
Figure 14.6-3 8-bit Serial Output Operation
■ Operation at Serial Output Completion
At the rising edge of the shift clock for serial data of the 8th bit, the interrupt request flag bit (SMR: SIOF)
is set to "1" and the serial I/O start bit (SMR: SST) is set (cleared) to "0".
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
SMR SIOF SIOE SCKE SOE CKS1 CKS0 BDS SST
0 1 1 1 1
SDR
DDR3
0
SSEL SSEL
1
0
1
Transmission data setting
: Used bit
: Unused bit
: Set "0"
: Set "1"
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
SDR #7 #6 #5 #4 #3 #2 #1 #0
#0 #1 #2 #4 #3 #5 #6 #7
0 7 6 5 4 3 2 1
For LSB first
SO pin
Serial output data
Shift clock
Clear via program
SIOF bit
SST bit
Interrupt request
Automatic clear at transfer end
Transfer start