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3 timer 1 control register (tcr1), Timer 1 control register (tcr1) – FUJITSU F2MC-8L F202RA User Manual

Page 191

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175

CHAPTER 8 8/16-BIT CAPTURE TIMER/COUNTER

8.4.3

Timer 1 Control Register (TCR1)

The timer 1 control register (TCR1) is used to select functions, allow and prohibit
operation, control interrupts, and check interrupt states in timer 1 for the 8-bit mode of
the 8/16-bit capture timer/counter. When used in the 16-bit mode, TCR1 is controlled by
the timer 0 control register (TCR0), but TCR1 setting is required.

Timer 1 Control Register (TCR1)

Figure 8.4-4 Timer 1 Control Register (TCR1)

4t

IN

S

T

[1.2

8

µ

s

]

T

S

TR1

0

TC

S

12 TC

S

11 TC

S

10

0

0

0

0

0

1

0

1

0

0

1

1

1

0

0

1

0

1

1

1

0

1

1

1

T1IEN

0

1

TFCR1

0

TIF1

0

b

it7

b

it6

b

it5

b

it4

b

it

3

b

it2

b

it1

b

it0

TIF1 TFCR1 T1IEN

TC

S

12 TC

S

11 TC

S

10 T

S

TR1

R

R/W

R/W

R/W

R/W

R/W

R/W

R/W : Re

a

d

ab

le/Writ

ab

le

R

: Re

a

d only

: Initi

a

l v

a

l

u

e

1

1

1

Addre

ss

Initi

a

l v

a

l

u

e

Timer

s

t

a

rt

b

it

The co

u

nter oper

a

tion i

s

s

topped.

The co

u

nter i

s

cle

a

red

a

nd increment i

s

s

t

a

rted.

Clock

s

o

u

rce

s

election

b

it

s

(o

s

cill

a

tion: 12.5 MHz)

16-

b

it mode

Interr

u

pt re

qu

e

s

t en

ab

le

b

it

Interr

u

pt re

qu

e

s

t o

u

tp

u

t i

s

prohi

b

ited.

Interr

u

pt re

qu

e

s

t o

u

tp

u

t i

s

a

llowed.

Comp

a

re m

a

tch detection fl

a

g cle

a

r

b

it

Not

a

ffected (

a

t re

a

d,

a

lw

a

y

s

"0")

The comp

a

re m

a

tch detection fl

a

g i

s

cle

a

red.

Comp

a

re m

a

tch detection fl

a

g

b

it

A comp

a

re m

a

tch h

as

not occ

u

rred.

A comp

a

re m

a

tch h

as

occ

u

rred.

001A

H

2t

IN

S

T

[0.64

µ

s

]

16t

IN

S

T

[5.12

µ

s

]

64t

IN

S

T

[20.4

8

µ

s

]

12

8

t

IN

S

T

[40.96

µ

s

]

256t

IN

S

T

[

8

1.92

µ

s

]

512t

IN

S

T

[16

3

.

8

4

µ

s

]

000-0000

B

t

IN

S

T

: In

s

tr

u

ction cycle (Affected

b

y the clock mode

a

nd other

s

.)

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