FUJITSU F2MC-8L F202RA - Manual (Page 111)

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CHAPTER 4 I/O PORTS
■ Block Diagram of Port 5
Figure 4.5-1 Block Diagram of Port 5
■ Registers of Port 5
The registers PDR5, DDR5, and PUL5 are associated with port 5.
One of the bits of these registers corresponds to one pin of port 5.
Table 4.5-2 tabulates the correspondence between the pin and a bit of the port 5 registers.
DDR
P-ch
N-ch
PDR
PUL
Inter
n
a
l d
a
t
a
bu
s
PDR re a d
PDR re a d
(when re a d-modify-write i s
performed)
O u tp u t l a tch
PDR write
DDR write
PUL re a d
S top mode ( S PL = 1)
O u tp u t from
peripher a l
O u tp u t
en ab le
from
peripher a l
P u ll- u p re s i s tor
Pin
S top mode ( S PL = 1)
PUL write
DDR re a d
Table 4.5-2 Correspondence between the Pin and a Bit of the Port 5 Registers
Port name Bits of associated registers and corresponding pins
Port 5
PDR5, DDR5, PUL5 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Pin corresponding to bit - - - - - - - P50