1 registers of port 0 (pdr0, ddr0, and pul0), Registers of port 0 (pdr0, ddr0, and pul0) – FUJITSU F2MC-8L F202RA User Manual
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CHAPTER 4 I/O PORTS
4.2.1
Registers of Port 0 (PDR0, DDR0, and PUL0)
This section describes the registers associated with port 0.
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Functions of Port 0 Registers
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Port 0 data register (PDR0)
The PDR0 register indicates the state of the output latch. For a pin set to function as an output port, the
same value ("0" or "1") as the value state of the output pin can be read from this register. If the pin is set to
function as an input port, however, its output latch value cannot be read from the register.
Note:
When a bit manipulation instruction (SETB, CLRB) is executed, the output latch values, not the value
states of the pins, are read; thus, output latch values, other than those for bits to be manipulated, do not
change.
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Port 0 data direction register (DDR0)
The DDR0 register sets the I/O direction of each pin per bit.
When a bit of the DDR0 register corresponding to a pin of port 0 is set to "1", the pin functions as an output
port. When the bit is set to "0", the pin functions as an input port.
Note:
Because the DDR0 register is write only, bit manipulation instructions (SETB, CLRB) do not apply.
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Setting a port pin to serve external interrupt inputs
If a pin of port 0 is used as an external interrupt input pin, enable the external interrupt circuit operation and
set the pin to function as an input port. When the pin is set in this mode, its output latch value has no
significance.
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Setting a port pin to serve analog inputs
If a pin of port 0 is used as an analog input pin, write "0" for the bit corresponding to the pin on the DDR0
register. The output transistor is then set to OFF and the pin is set in the Hi-Z state.
Set the bit of the ADEN register of the A/D converter to "1", the bit corresponding to the analog input pin
in use.
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Setting the input to a peripheral enable
If a peripheral with an input pin is used, set the pin of port 0 for the input to the peripheral to function as an
input port. In this mode, the corresponding output latch value has no significance.