FUJITSU F2MC-8L F202RA - Manual (Page 64)

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CHAPTER 3 CPU
3.5.3 Reset Operation
The CPU reads the mode data (mode fetch) and reset vector from internal ROM
according to the mode pin settings following the cancellation of a reset. For a return
triggered by a reset when power is turned on and in stop mode, the CPU fetches the
mode after oscillation stabilization wait time has expired. When a reset occurs, the
contents in RAM cannot be guaranteed.
■ Overview of the Reset Operation
Figure 3.5-3 Reset Operation Flow
YES
YES
NO
YES
NO
Software reset
Watchdog reset External reset input Power-on reset
Power-on
reset selected?
When power
is turned on or in stop
mode?
State of reset wait-
ing for stabilization
of oscillation
External reset
state cancelled?
Mode data fetch
State of reset wait-
ing for stabilization
of oscillation State of reset wait-
ing for stabilization
of oscillation
Reset vector fetch
Instruction code fetched from the address that
indicates the reset vector; the instruction is then
executed.
Being reset
Mode fetch
(reset operation)
Normal operation
(RUN mode)