FUJITSU F2MC-8L F202RA - Manual (Page 238)

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CHAPTER 9 12-BIT PPG TIMER
Figure 9.6-1 Setting Change during 12-bit PPG Timer Operation
● Error
Because the counter start by program is asynchronous with the count-up start by the selected count clock,
an error (a time difference) may occur until detection of synchronization of compare values for the "H"
width and for the cycle period with a count by the counter. A major error may shorten the time before the
above synchronization to one count clock cycle.
Figure 9.6-2 illustrates an error (a time difference) before the count operation start.
Figure 9.6-2 Error before Count Operation Start
(RCR23,24:SCL0 to SCL11)
(RCR21,22:HSC0 to HSC11)
"FFF"
H
* 3
* 2
* 1
* 1
"00" H
Overflow
Cycle period setting
"H" width setting
Count by counter
Extend by overflow 1 period
PPG output pulse waveform
Because the count interval of the operating counter is less than the changed setting, the setting is
effective only within the cycle.
* 1:
* 2: Because a cycle period less than the count interval of the operating counter is set, synchronization
is not detected and the counter overflows.
* 3: Because an "H" width less the count interval of the operating counter is set, synchronization is not
detected until the next cycle.
0 1 2 3 4
Count by counter
Count clock
1 cycle
Count 0
period
Counter start
Error
(time
difference)