Altera CPRI IP Core User Manual
User guide cpri megacore function
Table of contents
Document Outline
- 13.1CPRI MegaCore Function User Guide
- Contents
- 1. About This MegaCore Function
- 2. Getting Started
- 3. Parameter Settings
- 4. Functional Description
- Architecture Overview
- Clocking Structure
- Reset Requirements
- MAP Interface
- Auxiliary Interface
- Media Independent Interface to an External Ethernet Block
- CPU Interface
- CPRI Protocol Interface Layer (Physical Layer)
- 5. Testing Features
- 6. Signals
- 7. Software Interface
- 8. CPRI IP Core Demonstration Testbench
- A. Initialization Sequence
- B. Implementing CPRI Link Autorate Negotiation
- C. CPRI Autorate Negotiation Testbench
- D. Advanced AxC Mapping Modes
- E. Delay Measurement and Calibration
- Delay Measurement and Calibration Features
- Delay Requirements
- Single-Hop Delay Measurement
- Rx Path Delay
- Tx Path Delay
- Toffset
- Round-Trip Delay
- Round-Trip Cable Delay
- Tx Bitslip Delay in the Round-Trip Delay Calculation
- Dynamic Pipelining for Automatic Round-Trip Delay Calibration
- Round-Trip and Cable Delay Calculation Examples
- Round-Trip and Cable Delay Calculation Example 1: Two Stratix IV GX Devices
- Round-Trip and Cable Delay Calculation Example 2: Two Arria II GX Devices
- Round-Trip and Cable Delay Calculation Example 3: Two Different Device Families
- Round-Trip and Cable Delay Calculation Example 4: Two Different Device Families
- Multi-Hop Delay Measurement
- F. Integrating the CPRI IP Core Timing Constraints in the Full Design
- G. Porting a CPRI IP Core from the Previous Version of the Software
- Additional Information