Altera CPRI IP Core - Manual (Page 200)

E–22 Appendix E: Delay Measurement and Calibration
Single-Hop Delay Measurement
CPRI MegaCore Function December 2013 Altera Corporation
User Guide
rx_bitslipboundaryselectout has a non-zero value, the correct value of
T_txv_RX is 7.025 cpri_clkout cycles.
The Rx buffer delay is 31 cpri_clkout cycles, yielding a total delay of 47.6
cpri_clkout cycles.
46.025 = <fixed transceiver delay> + <Rx buffer delay> + 0 + 3 + <fixed core delay>
= 7.025 + 31 + 0 + 3 + 5
6. For each of the REC master and the RE slave, read the value in the
tx_ex_buf_delay field of the CPRI_EX_DELAY_STATUS register (at register offset
0x40) and the value in the ex_delay field of the CPRI_EX_DELAY_CONFIG register.
Read the tx_ex_buf_delay field only after the ex_buf_delay_valid bit in the
register is high.
7. For each of the REC master and the RE slave, divide the value in the
tx_ex_buf_delay register field by the value in the ex_delay register field. The
result is the current Tx elastic buffer delay in cpri_clkout cycles. In this example,
the Tx elastic buffer delay in the REC master is 6.5 cpri_clkout cycles, and the Tx
elastic buffer delay in the RE slave is 7.5 cpri_clkout cycles.
8. Calculate the Tx path delay through the REC master.
In this example, the value in the tx_bitslipboundaryselect field of the
CPRI_TX_BITSLIP register is 0. Therefore, according to Table E–7 on page E–16 , the
correct value of T_txv_TX is 3.6 cpri_clkout cycles.
According to Table E–6 on page E–14 , the correct value of T_T4 is 7 cpri_clkout
cycles. You calculated the Tx elastic buffer delay in steps 6 and 7 .
Tx path delay = T_T4 + <Tx elastic buffer delay> + T_txv_TX = 7 + 6.5 + 3.6 = 17.1
9. Calculate the Tx path delay through the RE slave.
In this example, the value in the tx_bitslipboundaryselect field of the
CPRI_TX_BITSLIP register is 0xE (decimal 14). Therefore, according to Table E–7 on
page E–16 , the correct value of T_txv_TX is 3.95 cpri_clkout cycles.
Because the device family is the same for the REC master and the RE slave in this
example, they have the same T_T4 delay. You calculated the Tx elastic buffer delay
in steps
6 and 7 .
Tx path delay = T_T4 + <Tx elastic buffer delay> + T_txv_TX = 7 + 7.5 + 3.95 = 18.45
10. Calculate
T14 = rx_round_trip_delay – <REC Rx path delay> – <REC Tx path delay>
= 109 – 46.025 – 17.1
= 45.875
cpri_clkout cycles
11. Calculate
Toffset = <RE Rx path delay> + + delay>,
= 25.5 + 18.45 + 1
= 44.95
cpri_clkout cycles
12. Perform the final calculation. Calculate
Round-trip cable delay = T14 – Toffset
= 45.875 – 44.95
= 0.925
cpri_clkout cycles