Altera CPRI IP Core - Manual (Page 100)

6–2 Chapter 6: Signals
MAP Interface Signals
CPRI MegaCore Function December 2013 Altera Corporation
User Guide
map{23…0}_rx_ready Input
Read-ready signal for each antenna-carrier interface, in FIFO mode.
Indicates to the CPRI IP core that the application is ready to receive
data on the corresponding data channel in the next clock cycle.
Asserted by the sink to mark ready cycles, which are cycles in which
transfers can occur. If ready is asserted on cycle N, the cycle
(N+
READY_LATENCY ) is a ready cycle. The MAP receiver interface in
FIFO mode is designed for READY_LATENCY equal to 1.
In synchronous buffer mode, the application must hold the
mapN_rx_ready signals high continuously.
In the internally-clocked mode, the CPRI IP core ignores this signal.
map{23…0}_rx_data[31:0] Output
32-bit read data being transmitted on each antenna-carrier interface.
Bits [15:0] are the I component of the IQ sample. Bits [31:16] are the Q
component of the IQ sample.
In FIFO mode, data is valid as early as one mapN_rx_clk clock cycle
after the application asserts the read-ready input signal
mapN_rx_ready , but is only valid while the CPRI IP core asserts the
mapN_rx_valid signal .
In synchronous buffer mode, data is valid one mapN_rx_clk clock
cycle after the application asserts the mapN_rx_resync signal. To
ensure valid data in synchronous buffer mode, the application should
only assert the
mapN_rx_resync signal after the CPRI IP core asserts
the cpri_rx_start signal. However, the CPRI IP core does not
enforce this requirement.
In the internally-clocked mode, data is valid one cpri_clkout clock
cycle after the CPRI IP core asserts the mapN_rx_start output signal,
but is only valid while the CPRI IP core asserts the mapN_rx_valid
signal .
map{23…0}_rx_valid Output
Valid signal for FIFO mode and for the internally-clocked
synchronization mode.
In FIFO mode, this signal is asserted when the mapN Rx buffer
exceeds the threshold level in the
map_rx_ready_thr field of the
CPRI_MAP_RX_READY_THR register. Although each data channel has
its own mapN_rx_valid signal, all data channels use the same
map_rx_ready_thr threshold value. This signal qualifies all the other
output signals of the MAP receiver interface. On every rising edge of
the clock at which
mapN_rx_valid is high, mapN_rx_data can be
sampled.
In the internally-clocked mode, the CPRI IP core asserts each
mapN_rx_valid signal one cpri_clkout clock cycle after it asserts
the corresponding mapN_rx_start signal.
In synchronous buffer mode,the map{23...0}_rx_valid signals do
not participate in data transfer synchronization, and the application
should ignore these signals.
Table 6–1. MAP Receiver Interface Signals (Part 2 of 3)
Signal Direction Description