Altera CPRI IP Core - Manual (Page 155)

December 2013 Altera Corporation CPRI MegaCore Function
User Guide
A. Initialization Sequence
This appendix describes the most basic initialization sequence for an Altera CPRI IP
core.
To initialize the CPRI IP core, perform the following steps:
1. To configure the Altera FPGA with your design, download your .sof file to the
FPGA.
2. Perform the following two actions simultaneously:
■ Perform a global CPRI IP core reset by asserting the following reset signals
simultaneously, holding them asserted for at least three cycles of the slowest
associated clock, and deasserting each as soon as possible thereafter:
■ config_reset
■ cpu_reset
■ reset
■ reset_ex_delay
■ mapN_rx_reset , for the appropriate values of N
■ mapN_tx_reset , for the appropriate values of N
■ To reset, power down, and power back up the high-speed transceiver in
variations that include an ALTGX megafunction, assert the
gxb_powerdown
signal. This signal is not available in variations that target an Arria V,
Cyclone V, or Stratix V device.
3. Write the value 0x21 to the CPRI_CONFIG register ( 0x8 ). This CPRI_CONFIG register
setting enables the CPRI IP core to start sending K28.5 symbols on the CPRI link.
4. Observe the cpri_rx_state output signal as it transitions from value 0x0 to value
0x2 to value 0x3. When it has value 0x3, and the cpri_rx_cnt_sync output signal
has value 0x1, the CPRI IP core CPRI receiver interface is in the HFNSYNC state.
The
cpri_rx_state output signal appears on extended_rx_status_data[1:0] and
the cpri_rx_cnt_sync output signal appears on extended_rx_status_data[4:2] .
5. Observe the cpri_rx_hfn_state output signal as it transitions to value 1. When it
has value 1, the hyperframe number is initialized. The cpri_rx_hfn_state output
signal appears on extended_rx_status_data[7] .
6. Observe the cpri_rx_bfn_state output signal as it transitions to value 1. When it
has value 1, the basic frame number is initialized. The cpri_rx_bfn_state output
signal appears on extended_rx_status_data[6] .
The CPRI IP core can now receive and transmit data on the CPRI link, on the
antenna-carrier interfaces, and on the auxiliary AUX interface.
To access the registers, the system requires an Avalon-MM master, for example a
Nios II processor. The Avalon-MM master can program these registers.