Altera CPRI IP Core - Manual (Page 143)

Chapter 7: Software Interface 7–27
HDLC Registers
December 2013 Altera Corporation CPRI MegaCore Function
User Guide
HDLC Registers
This section lists the HDLC registers. Table 7–67 provides a memory map for the
HDLC registers. Table 7–68 through Table 7–81 describe the HDLC registers in the
CPRI IP core.
1 If you turn off the Include HDLC block parameter, your application cannot access the
HDLC registers. In that case, attempts to access these registers read zeroes and do not
write successfully, as for a Reserved register address.
For more information about these registers, refer to “Accessing the HDLC Channel”
on page 4–50 .
Table 7–64. ETH_FWD_CONFIG—Ethernet Forwarding Configuration—Offset: 0x244
Field Bits Access Function Default
RSRV [31:17] UR0 Reserved. 15’h0
tx_start_thr [16:1] RW
Transmit start threshold. If store-and-forward mode is disabled,
transmission to the CPRI link starts when this number of 32-bit
words are stored in the Tx buffer.
16’h0004
tx_st_fwd [0] RW
Transmit store-and-forward mode. In store-and-forward mode, a
full packet is stored in the Tx buffer before transmission starts.
Packets longer than the Tx buffer are aborted.
1'h0
Table 7–65. ETH_CNT_RX_FRAME—Ethernet Receiver Module Frame Counter—Offset: 0x248
Field Bits Access Function Default
eth_cnt_rx_frame [31:0] RO Number of frames received from the CPRI receiver. 32'h0
Table 7–66. ETH_CNT_TX_FRAME—Ethernet Transmitter Module Frame Counter—Offset: 0x24C
Field Bits Access Function Default
eth_cnt_tx_frame [31:0] RO Number of frame transmitted to the CPRI transmitter. 32'h0
Table 7–67. CPRI HDLC Registers Memory Map (Part 1 of 2)
Address Name Expanded Name
0x300 HDLC_RX_STATUS HDLC Receiver Module Status
0x304 HDLC_TX_STATUS HDLC Transmitter Module Status
0x308 HDLC_CONFIG_1 HDLC Feature Configuration 1
0x30C HDLC_CONFIG_2 HDLC Feature Configuration 2
0x310 HDLC_RX_CONTROL HDLC Rx Control
0x314 HDLC_RX_DATA HDLC Rx Data
0x318 HDLC_RX_DATA_WAIT HDLC Rx Data With Wait-State Insertion
0x31C HDLC_TX_CONTROL HDLC Tx Control
0x320 HDLC_TX_DATA HDLC Tx Data
0x324 HDLC_TX_DATA_WAIT HDLC Tx Data With Wait-State Insertion
0x328 HDLC_RX_EX_STATUS HDLC Rx Additional Status