Altera CPRI IP Core User Manual
Page 187
Appendix E: Delay Measurement and Calibration
E–9
Single-Hop Delay Measurement
December 2013
Altera Corporation
CPRI MegaCore Function
User Guide
3. Read the value of the
CPRI_EX_DELAY_STATUS
register at offset 0x40 (
).
If the
ex_buf_delay_valid
field of the register is set to 1, the value in the
rx_ex_buf_delay
field has been updated, and you can use it in the following
calculations. For this example, assume the value read from the
rx_ex_buf_delay
field is 0x107D, which is decimal 4221.
4. Perform the following calculation to determine the delay through the Rx elastic
buffer:
Delay through Rx elastic buffer = (
rx_ex_buf_delay
×
cpri_clkout
period) / N
= (4221 × 13.02083 ns) / 127
= 432.7632 ns
This delay comprises (432.7632 ns / 13.02083 ns) = 33.236
cpri_clkout
clock
cycles.
These numbers provide you the result for this particular example. For illustration,
the preceding calculation shows the result in nanoseconds. You can derive the
result in
cpri_clkout
clock cycles by dividing the preceding result by the
cpri_clkout
clock period. Alternatively, you can calculate the number of
cpri_clkout
clock cycles of delay through the Rx elastic buffer directly, as
rx_ex_buf_delay
/ N.
Calculation Example: Rx Path Delay to AUX Output
This section shows you how to calculate the Rx path delay to the AUX output, based
on the example shown in
“Calculation Example: Rx Buffer Delay” on page E–8
. This
example walks through the calculation for the case of a CPRI IP core that runs at CPRI
data rate 3072 Mbps and targets an Arria II GX device. The
cal_en
field of the
CPRI_AUTO_CAL
register has the value of 0 and the
tx_bitslipboundaryselect
and
rx_bitslipboundaryselectout
fields of the
CPRI_TX_BITSLIP
register have the value
of 0.
To calculate the Rx path delay, perform the following steps:
1. Consult
Table E–1 on page E–5
for the correct value of T_txv_RX for your device
family. For the example, the table yields T_txv_RX = 5.7
cpri_clkout
clock cycles.
2. Calculate the latency through the Rx Receive buffer, including phase alignment, by
“Calculation Example: Rx Buffer Delay” on page E–8
for
your CPRI IP core instance. For the example, the calculations shown in
“Calculation Example: Rx Buffer Delay”
yield a delay through the Rx Receive
buffer of 33.236
cpri_clkout
clock cycles.
3. Read the value in the
rx_byte_delay
field of the
CPRI_RX_DELAY
register—when
the value in
rx_byte_delay
is non-zero, a byte alignment delay of one
cpri_clkout
cycle occurs in the Rx path. When the value is zero, no byte
alignment delay occurs. In this example, the value in the
rx_byte_delay
field is 0.
4. Read the value of the
cal_pointer
field of the
CPRI_AUTO_CAL
register. In this case,
the value in this field is 3. This value is consistent with the fact that the
cal_en
field
of the
CPRI_AUTO_CAL
register has the value of 0.
5. Consult
Table E–3 on page E–8
to determine the delay through the CPRI IP core to
the AUX interface. For the example, the duration of this delay is 5
cpri_clkout
clock cycles.