Transmitting ethernet traffic, Transmitting ethernet traffic –48 – Altera CPRI IP Core User Manual
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4–48
Chapter 4: Functional Description
CPU Interface
CPRI MegaCore Function
December 2013
Altera Corporation
User Guide
The CPRI specification dictates that a CPRI hyperframe that contains Ethernet data
also contain a pointer to the start of that data in control byte Z.194.0. The pointer value
0x0 indicates that no Ethernet channel is supported in the current hyperframe. A valid
pointer holds a subchannel index value between 0x14 and 0x3F, inclusive. The length
of the Ethernet data can extend beyond the end of the hyperframe; if a received
Ethernet frame exceeds 1536 bytes, the Ethernet module resets, unless the
rx_long_frame_en
bit of the
ETH_CONFIG_1
register is set.
The CPRI transmitter reads the pointer value from the
tx_fast_cm_ptr
field of the
CPRI_CM_CONFIG
register and writes it in CPRI control byte Z.194.0 in the outgoing
CPRI hyperframe. The
rx_fast_cm_ptr
field of the
CPRI_CM_STATUS
register holds the
current pointer value, determined during the software set-up sequence or by dynamic
modification, in which the same new pointer value is received in CPRI control byte
Z.194.0 four hyperframes in a row.
Software can configure the Ethernet channel by writing to the
ETH_CONFIG_1
register
through the CPRI IP core Avalon-MM CPU interface. For additional information
about this register, refer to
Transmitting Ethernet Traffic
To transmit an Ethernet frame, the CPRI IP core must load the frame in a Tx Ethernet
buffer. Application software can direct the CPRI IP core to load the Ethernet frame in
the Tx Ethernet buffer by reading and writing the following registers:
■
ETH_CONFIG_2
register at offset 0x20C (
)—Configure the
CPRI IP core to automatically calculate the Frame check sequence and insert it at
the end of the frame data, by setting the
crc_enable
field in bit 0 of this register.
■
ETH_TX_STATUS
register at offset 0x204 (
)—Poll the
tx_ready_block
and
tx_ready
fields of this register. If the
tx_ready
field has a
value of 1, you can load a 4-byte word to the Tx Ethernet buffer. If the
tx_ready_block
field has a value of 1, you can load a block of eight 4-byte entries
to the Tx Ethernet buffer without polling the
tx_block_ready
or
tx_ready
bits
between CPU write operations.
■
ETH_TX_DATA
register at offset 0x220 (
)—Load data in this
register. To load a block of eight 4-byte entries to the Tx Ethernet buffer, you must
execute eight CPU write operations to this register.
■
ETH_TX_CONTROL
register at offset 0x21C (
)—Before you
load the final word of an Ethernet frame in the
ETH_TX_DATA
register (or
ETH_TX_DATA_WAIT
register (
)), set the
tx_eop
field and
write the
tx_length
field of this register to indicate how many bytes in the final
word are padding.
The Ethernet Tx buffer holds 64 4-byte entries, for a total of 256 bytes. When
transmitting Ethernet frames larger than the capacity of the Tx Ethernet buffer, you
must ensure you do not overflow or underflow the buffer. If the Ethernet transmitter
module writes data to the
ETH_TX_DATA
register when the Ethernet Tx buffer is not
ready, the
tx_abort
bit is set in the
ETH_TX_STATUS
register and the current Ethernet
packet is aborted. To prevent the Ethernet transmitter module from aborting a frame,
you can write the data to the
ETH_TX_DATA_WAIT
register. The
ETH_TX_DATA_WAIT
register can accept data when the Ethernet Tx buffer is not ready for new data.