Altera CPRI IP Core User Manual
Page 68

4–36
Chapter 4: Functional Description
Auxiliary Interface
CPRI MegaCore Function
December 2013
Altera Corporation
User Guide
The CPRI IP core passes the incoming AUX data through to the CPRI link
unmodified. You must ensure that the incoming AUX data bits already include any
CRC values expected by the application at the other end of the CPRI link.
The CPRI transmitter frame synchronization state machine provides the following
data and synchronization signals on the AUX interface to enable the required precise
frame timing:
■
cpri_tx_start
—asserted for the duration of the first basic frame following the
offset defined in the
CPRI_START_OFFSET_TX
register
■
cpri_tx_rfp
and
cpri_tx_hfp
—synchronization pulses for start of 10 ms radio
frame and start of hyperframe
■
cpri_tx_bfn
and
cpri_tx_hfn
—current radio frame and hyperframe numbers
■
cpri_tx_x
—index number of the current basic frame in the current hyperframe
■
cpri_tx_seq
—index number of the current 32-bit word in the current basic frame
■
cpri_tx_aux_data
—incoming data port for data on the AUX link
■
cpri_tx_aux_mask
—incoming bit mask for AUX link data that indicates bits that
must be transmitted without changes to the CPRI link
The CPRI IP core layer 1 uses the
cpri_tx_aux_mask
to select the enabled bit
values in the control transmit table. When mask bits are set, the corresponding
data bits from the AUX interface fill the CPRI frame, overriding any
internally-generated information. You must deassert all the mask bits during
K28.5 character insertion in the outgoing CPRI frame (which occurs when Z=X=0).
Otherwise, the CPRI IP core asserts an error signal
cpri_tx_error
on the
following
cpri_clkout
clock cycle to indicate that the K28.5 character expected by
the CPRI link protocol has been overwritten. You must also ensure you do not
override synchronization counter values in the control word.
The AUX transmitter module also receives a synchronization pulse in an REC master.
Application software can pulse the
cpri_tx_sync_rfp
input signal to resynchronize
the 10 ms radio frame. Asserting this signal resets the frame synchronization machine
in an REC master.
In response to the rising edge of its
cpri_tx_sync_rfp
input signal
(
aux_tx_mask_data[64]
), a CPRI REC master IP core restarts the 10 ms radio frame.
The rising edge of the
cpri_tx_sync_rfp
signal must be synchronous with the
cpri_clkout
clock. On the seventh
cpri_clkout
cycle following a
cpri_tx_sync_rfp
pulse, the
cpri_tx_hfp
and
cpri_tx_rfp
signals pulse, the
cpri_tx_x
and
cpri_tx_hfn
signals have the value 0, and the
cpri_tx_bfn
signal increments from its