Altera CPRI IP Core - Manual (Page 174)

D–2 Appendix D: Advanced AxC Mapping Modes
Advanced Mapping Mode Similarities and Differences
CPRI MegaCore Function December 2013 Altera Corporation
User Guide
All of the advanced AxC mapping modes comply with the description in Section
4.2.7.2.4 of the CPRI V4.2 Specification. Advanced mapping modes 01 and 11 comply
with two different interpretations of Section 4.2.7.2.5. Advanced mapping mode 11 is
available in Quartus II software releases prior to release 11.1 as advanced mapping
mode 01, and the current advanced mapping mode 01 is new in the Quartus II
software release 11.1.
In the Advanced 1 and Advanced 2 mapping modes, each IQ data sample is
considered a different AxC container, for backward compatibility with earlier
versions of the CPRI specification. However, multiple consecutive 32-bit words in the
same frame may contain data samples from or for the same AxC interface. In other
words, data to or from the same AxC interface may appear in consecutive timeslots,
even though these IQ data samples are considered individual AxC containers. IQ data
samples do not span frames. Spare bytes not assigned to an AxC container become
reserved bits. These reserved bits are located at the end of the basic frame.
Advanced Mapping Mode Similarities and Differences
This section describes the similarities and differences between the different advanced
mapping modes. In each advanced mapping mode, the behavior is different in the
15-bit and 16-bit modes.
Figure D–1 on page D–4 illustrates an example in this section
that describes the differences between the advanced mapping modes in 15-bit mode,
and
Figure D–2 on page D–5 illustrates an example of the supported advanced
mapping modes in 16-bit mode.
In the advanced mapping modes, AxC containers are packed in the IQ data block in a
flexible position (Option 2), as illustrated in Section 4.2.7.2.3 of the CPRI V4.2
Specification. Configuration tables define the mapping of AxC containers to offsets in
the AxC interface timeslots.
You specify the flexible position of the start of an AxC container in its timeslot using
the Rx and Tx mapping tables. You configure the Rx and Tx mapping tables through
the CPU interface. You can configure one mapping table entry at a time. The table
index specified in the
map_conf_index field of the CPRI_MAP_TBL_INDEX register
determines the Rx and Tx mapping table entries that appear in the CPRI_MAP_TBL_RX
and CPRI_MAP_TBL_TX registers, respectively.The CPRI_MAP_TBL_RX register holds the
currently configurable entry in the Rx mapping table, and the CPRI_MAP_TBL_TX
register holds the currently configurable entry in the Tx mapping table. You must
configure these tables prior to data transmission on the MAP interface, otherwise data
loss may occur.
Each table entry corresponds to an IQ data sample in one AxC container block. Each
table entry has an enable bit and a field in which to specify the AxC interface number
for the current IQ data sample, in addition to a
position field which specifies the
starting bit position of the IQ sample in the timeslot — the current 32-bit word on the
AxC interface — and a
width field to specify the number of bits in the current data
sample.
The application can specify an offset for the start of an AxC container in a timeslot; the
position field of the table entry that corresponds to the timeslot in which that AxC
container begins transmission (in the CPRI Rx direction) or appears on the data
channel (in the CPRI Tx direction), holds this offset. The offset is specified in bits.