Altera CPRI IP Core - Manual (Page 82)

4–50 Chapter 4: Functional Description
CPU Interface
CPRI MegaCore Function December 2013 Altera Corporation
User Guide
■ Multicast filtering: if the least significant bit of the first destination MAC address
byte, the group address bit, is set to 1, use the
ETH_HASH_TABLE register to
determine whether to accept this destination MAC address. Because the hash
algorithm might not filter the destination address as intended, you must
implement full address validation in software if you enable multicast filtering. To
enable multicast filtering, set the
multicast_flt_en bit of the ETH_CONFIG_1
register.
■ Broadcast filtering: accept all packets with destination MAC address
0xFFFFFFFFFFFF, the Ethernet broadcast address. To enable broadcast filtering, set
the
broadcast_en bit of the ETH_CONFIG_1 register.
Ethernet Rx Buffer Status
The CPRI IP core reports relevant Ethernet Rx buffer status to the CPU interface by
updating the following fields of the
ETH_RX_STATUS register:
■ The ETH_RX_STATUS rx_ready bit indicates that at least one word of data is
available in the Ethernet Rx buffer and ready to be read.
■ The ETH_RX_STATUS rx_eop bit indicates that the next ready data word contains
the end-of-packet byte.
■ The ETH_RX_STATUS rx_length field indicates the number of valid bytes in the
end-of-packet word.
■ The ETH_RX_STATUS rx_abort bit indicates that the current received packet is
aborted.
■ The ETH_RX_STATUS rx_ready_block bit indicates that the next block of packet
data is ready to be read and does not contain the end-of-packet byte.
■ The ETH_RX_STATUS rx_ready_end bit indicates that the end-of-packet byte is
ready in the Ethernet Rx buffer.
Software can set the ETH_RX_CONTROL rx_discard bit to abort the current received
packet. The Ethernet receiver ensures that following read from the Ethernet Rx buffer
is a start-of-packet word.
Ethernet Data Transfer
The next ready data word is available in the ETH_RX_DATA and ETH_RX_DATA_WAIT
registers. If no Ethernet data word is ready, reading from the ETH_RX_DATA_WAIT
register inserts wait states in the Ethernet channel. If no Ethernet data word is ready,
reading from the
ETH_RX_DATA register causes the rx_abort bit to be set. The CPU
interface receiver module reads the Ethernet packet data one word at a time from one
of these registers.
Accessing the HDLC Channel
If you turn on the Include HDLC block parameter, your CPRI IP core includes an
internal High-Level Data Link Controller (HDLC) block. If you turn off this
parameter, the internal HDLC block is not available and your application cannot
access the HDLC registers. If the internal HDLC block is turned off, attempts to access
these registers read zeroes and do not write successfully, as for a reserved register
address.