Altera CPRI IP Core - Manual (Page 103)

Chapter 6: Signals 6–5
Auxiliary Interface Signals
December 2013 Altera Corporation CPRI MegaCore Function
User Guide
Auxiliary Interface Signals
Table 6–3 through Table 6–4 list the signals on the CPRI IP core auxiliary interface. All
the signals in Table 6–3 through Table 6–4 are clocked by the internal clock visible on
the cpri_clkout port.
map{23…0}_tx_ready Output
Ready signal for each antenna-carrier interface.
In FIFO mode, the ready signal is asserted when the mapN Tx buffer falls
below the threshold level in the
map_tx_ready_thr field of the
CPRI_MAP_TX_READY_THR register. Although each data channel has its own
mapN_tx_ready signal, all data channels use the same map_tx_ready_thr
threshold value. Indicates that the CPRI IP core is ready to receive data on
the data channel in the current clock cycle. Asserted by the Avalon-ST sink to
mark ready cycles, which are the cycles in which transfers can take place. If
ready is asserted on cycle N, the cycle (N+
READY_LATENCY ) is a ready cycle.
In the MAP transmitter interface in FIFO mode, READY_LATENCY is equal to
0, so the cycle on which mapN_tx_ready is asserted is the ready cycle.
In the internally-clocked mode, the CPRI IP core asserts the ready signal one
cycle before the antenna-carrier interface is ready to receive data on the data
channel. In this mode,
READY_LATENCY is equal to 1.
In synchronous buffer mode, the map{23...0}_tx_ready signals do not
participate in data transfer synchronization, and the application should ignore
these signals.
map{23…0}_tx_resync Input
Resynchronization signal for use in synchronous buffer mode. This signal is
synchronous to the
mapN_tx_clk clock.
In FIFO mode the map{23...0}_tx_resync signals do not participate in
data transfer synchronization, and the CPRI IP core ignores these signals. In
the internally-clocked mode, these signals are not present.
map{23…0}_tx_status_data Output
This vector contains the following status bits:
[2] cpri_map_tx_overflow : Tx FIFO overflow indicator for this
antenna-carrier interface. This signal is synchronous to the
cpri_clkout clock, and is asserted following a write to a full
buffer. This signal reflects the value in the appropriate bit of the
buffer_tx_overflow field of the CPRI_IQ_TX_BUF_STATUS
register ( Table 7–49 on page 7–22 ).
[1] cpri_map_tx_underflow : Tx FIFO underflow indicator for this
antenna-carrier interface. This signal is synchronous to the
cpri_clkout clock, and is asserted following a read from an empty
buffer. This signal reflects the value in the appropriate bit of the
buffer_tx_underflow field of the CPRI_IQ_TX_BUF_STATUS
register ( Table 7–49 on page 7–22 ).
[0] cpri_map_tx_en : Indicates that this antenna-carrier interface is
enabled. The value is determined in the CPRI_IQ_TX_BUF_CONTROL
register. Use this signal to disable external logic for inactive AxC
interfaces and to map interface clock gating to save power.
Table 6–2. MAP Transmitter Interface Signals (Part 2 of 2)
Signal Direction Description