Altera CPRI IP Core - Manual (Page 202)

E–24 Appendix E: Delay Measurement and Calibration
Single-Hop Delay Measurement
CPRI MegaCore Function December 2013 Altera Corporation
User Guide
Round-Trip and Cable Delay Calculation Example 3: Two Different Device
Families
This example shows the calculation for the case of two link partner CPRI IP cores
configured with autorate negotiation enabled in a single-hop configuration, running
at CPRI data rate 3.072 Gbps. The REC master is configured on a Stratix IV GX device
and the RE slave is configured on an Arria II GX device. In both devices, the
cal_en
field of the CPRI_AUTO_CAL register has the value of 0 and the rx_byte_delay field of
the CPRI_RX_DELAY register has the value of 0.
The calculation is identical to the calculation in Examples 1 and 2, except that the fixed
and transceiver delays are different for the two different devices, so the fixed parts of
the Rx path delay and Tx path delay are different on the two devices. In addition,
Example 3 has a different value in the
rx_round_trip_delay register field. In your
own system, the Rx elastic buffer delay and Tx elastic buffer delay may also vary.
To calculate the round-trip cable delay in this system, perform the steps in
“Round-Trip and Cable Delay Calculation Example 1: Two Stratix IV GX Devices” ,
replacing values according to Table E–10 . The final row of Table E–10 shows the
calculated cable delay.