Altera CPRI IP Core - Manual (Page 74)

4–42 Chapter 4: Functional Description
CPU Interface
CPRI MegaCore Function December 2013 Altera Corporation
User Guide
Each of the three sources of input to the CPU interface communicates with the CPRI
IP core by reading and writing registers through a single Avalon-MM port on the CPU
interface. Arbitration among the different sources must occur outside the CPRI IP
core.
If the CPRI IP core is configured with an MII, the application cannot access the IP
core’s Ethernet registers through the CPU interface. However, if the HDLC block is
configured, you can access the IP core’s HDLC registers whether or not the MII is
configured.
For more information about the CPRI IP core registers, refer to Chapter 7, Software
Interface .
Accessing the Hyperframe Control Words
When you turn on the Include Vendor Specific Space (VSS) access through CPU
interface
option, you can access the 256 control words in a hyperframe through the
CPRI IP core CPU interface. The CPRI_CTRL_INDEX register ( Table 7–7 on page 7–5 )
and the CPRI_RX_CTRL register ( Table 7–8 on page 7–6 ) support your application in
reading the incoming control words, and the CPRI_CONFIG register ( Table 7–6 on
page 7–4 ), CPRI_CTRL_INDEX register, and CPRI_TX_CTRL register ( Table 7–9 on
page 7–6 ) support the application in writing to outgoing control words.
Register support provides you access to the full control word. Alternatively, in
timing-critical applications, you can access the full control words through the CPRI IP
core AUX interface.
1
Altera recommends that you use the CPU interface to access the hyperframe control
words only in applications that are not timing-critical.