Altera CPRI IP Core - Manual (Page 90)

4–58 Chapter 4: Functional Description
CPRI Protocol Interface Layer (Physical Layer)
CPRI MegaCore Function December 2013 Altera Corporation
User Guide
To acknowledge the reset request, the CPRI transmitter must send a reset
acknowledge on the CPRI link, by setting the Z.130.0 reset bit in five consecutive
outgoing hyperframes. If one of the acknowledgement conditions in
Table 4–16 holds,
the CPRI transmitter sends the reset acknowledge on the CPRI link. If the
reset_out_en bit of the CPRI_HW_RESET register is set, the CPRI IP core asserts the
external hw_reset_req signal until the reset occurs. This signal informs the
application layer of the low-level reset request.
After it transmits the five consecutive reset acknowledge bits, the CPRI transmitter
sets the
reset_gen_done and reset_gen_done_hold bits of its own CPRI_HW_RESET
register. If the reset_hw_en bit is set and the hw_reset_req signal is asserted, you must
set the hw_reset_assert signal, to tell the CPRI transmitter to send a reset
acknowledge on the CPRI link.
For more information about the CPRI_HW_RESET register, refer to Table 7–12 on
page 7–6 . For more information about the hw_reset_assert input signal, refer to
Table 6–15 on page 6–17 .
After reset, your software must perform link synchronization and other initialization
tasks. For information about the required initialization sequence following CPRI IP
core reset, refer to
Appendix A, Initialization Sequence .
Transmitter
The transmitter in the low-level interface transmits output to the CPRI link. This
module performs the following tasks:
■ Assembles data and control words in proper output format
■ Transmits standard frame sequence
■ Optionally scrambles the outgoing data transmission at 4915.2 Mbps,
6144.0 Mbps, and 9830.4 Mbps CPRI line rates
■ Inserts the following control words in their appropriate locations in the outgoing
hyperframe:
■ Synchronization control byte (K28.5) and filler bytes (D16.2) in the
synchronization control word
■ Hyperframe number (HFN)
■ Basic frame number (BFN)
■ HDLC bit rate
■ Pointer to start of Ethernet data in current frame
■ 4B/5B-encoded fast C&M Ethernet frames
■ Bit-stuffed slow C&M HDLC frames
■ Enabled control transmit table entries
■ Converts the data to the transceiver clock domain.
When no data is available to transmit on the CPRI link, the transmitter transmits the
standard frame sequence with zeroed control words and all-zero data.